- It provides extra rigidity with strong mechanical bonding between chip and the PCB’s corresponding connection, thus protecting solder joints from mechanical stress.
- It also helps transfer heat from highly-complex, high-power chips and sometimes acts as a heat sink.
- Also, as an efficient coefficient of thermal expansion (CTE) absorber and stress-relieving agents, underfill can help smaller packaging during thermal mismatching.
- Moreover, stress is dissipated throughout a device’s package, and the concentration of stress on the roots of the solder balls is avoided.
- Underfill also greatly improves the high-gravitational acceleration (High-G) performance, thermal-cycle performance, and fatigue cycle performance.
- Less than 500 cycles: very low requirements for thermal-cycle. SAC105 solder alloy (tin 98%, silver 1%, copper 0.5%) is enough to solve the problem without underfill. The micro BGA or micro CSP just needs to withstand the drop-test, usually a five-times drop test. Also, the standard SAC305 solder ball alloy needs to be changed to SAC105 solder ball alloy for all micro-BGA and micro-CSP components, but underfill doesn’t need to be used in this instance.
- 500 cycles: low requirement for thermal-cycle. High-material module underfill material is the perfect solution.
- 1,000 cycles: high requirement for thermal-cycle. Low-material module underfill material is perfect solution.
- 2,000 cycles: very high requirement for thermal-cycle. Requires a high-reliable connection between the CSP/FC die and board pads. Low-material module underfill material is perfect solution.
Underfill revisited: How a decades-old technique enables smaller, more durable PCBs
A well-orchestrated PCB design and assembly plan is required to successfully implement techniques such as underfill in next generation OEM embedded consumer and mobile designs.
Two distinct market sectors in embedded systems are driving a trend to ever smaller components that do more, do it more reliably, and do it while withstanding harsh conditions. In the consumer sector, both smaller size and increased functional densities are required for handheld, mobile, and portable systems, such as smart phones and tablets. In mil/aero portable electronics–such as satellites; unmanned aerial, undersea, and ground vehicles; and handheld, man pack, and small-form-factor battery-operated systems–ultra-reliability combined with the ability to withstand extreme temperatures and other environmental stresses are required in addition to greater functionality and reduced form factors.
Thus OEMs face ever-growing requirements for greater chip functionality, reduced size, mechanical toughness, and high reliability. To achieve smaller size, micro ball-grid arrays (BGAs) and chip scale packaging (CSP) are typical solutions (see Figure 1 for size comparisons). However, these smaller form factors mean greater design and assembly challenges, including extremely short solder joints and the requirement for greater stress relaxation for thermal stress. In a fine-pitch micro BGA, for instance, that pitch is at 0.3 millimeters (mm) and is rapidly moving to 0.25 mm. With the pitch decreasing, ball size is reduced. Consequently, the standoff height between the printed circuit board (PCB) and chip package is decreased. The shorter standoff height reduces PCB-level reliability. Hence, fine-pitch micro CSPs and micro BGAs have difficulty meeting mechanical shock and substrate flexing tests for portable electronics applications.
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Underfill to the rescue!
Underfill is a polymer or liquid applied on the PCB after it has been subjected to reflow. Basically, underfill encapsulates the bottom side of the silicon chip. The term “encapsulates” in PCB assembly parlance usually means covering the top surface of a device where fragile interconnects are located. But when speaking of underfill, encapsulate means to cover the fragile interconnects between the chip’s bottom side and the PCB’s top side (as shown in Figure 2). When underfill is used, mounting conventional CSP and BGA packaging onto the board using conventional assembly steps and techniques usually produce sound mechanical and thermal properties.
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Generally, underfill is dispensed on a corner or in a line along the edge of the micro BGA or micro CSP. Chip packages and PCB are then heated to the recommended temperature in the range of 125°C to 165°C to flow the underfill. Capillary action then takes over to absorb the underfill under the chip. Temperature is held until the underfill is cured. It takes about five minutes for fast-curing underfills to be completed. However, harder, more resilient underfills take upwards of an hour and a half to reach optimum strength. Figure 3 shows a typical underfill process for a micro BGA.
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Underfill is becoming increasingly popular because it solves a number of problems associated with smaller form factors:
Everything old is new again
Old timers may remember that several decades ago IBM Endicott Lab engineers came up with the “underfill effect” for their direct chip attach (DCA) or flip chips populating their PCBs. The technique was aimed at significantly pumping up performance by interposing adhesive between chip and substrate. Now, years later, it’s déjà vu all over again, as Yogi Berra once said. Reinforcement using underfill is becoming more popular because bonding reliability and package strength may decline as chip packaging shrinks and becomes more compact, and PCBs are made thinner and smaller.
Until recently, underfill was generally not necessary for typical device geometries and larger PCB assemblies. However, today PCBs are considerably smaller and must meet market demands for smaller and faster, with more features and functions. So today underfill is a critical PCB assembly process to ruggedize active components that are taking on Lilliputian dimensions. All indications point to a nonstop increase in device density and I/O pins from virtually every OEM front.
In a case where you have a combination of micro CSPs, micro BGAs, and an extremely high-reliability requirement, certain harsh environmental forces may deal a particular blow to a device’s solder bonds, creating faulty or nonexistent solder connections. But once underfill is applied, those package and board connections can be strengthened by as much as a factor of 10. Hence, the underfill process dramatically enhances thermal-cycling performance and shock resistance of those chip packaging and board connections.
Bear in mind that we’re dealing with ultra-fine pitch ball diameters of these miniscule packages, plus a fabrication land-pad diameter that is extremely small–most often less than nine mils, but in some cases less than four mils. So underfill is critical to compensate for the differences in thermal expansion rates of two unlike materials–solder joint and FR4 laminate materials. If the PCB designer doesn’t factor in underfill in today’s miniaturized board designs, the end product’s life expectancy can be significantly reduced by catastrophic interconnect cracking in the field.
Design and assembly engineers must work together
Today it’s crucial that the PCB design engineer work closely with assembly and manufacturing engineering to assure underfill of the correct amount and type are used in any given PCB project. There are two types of underfill materials. One is high-material module underfill, the other is low material module underfill material. High-material module underfill has an extremely low CTE, for instance Underfill-A CTE = 63 ppm/°C. The normal CTE data for this type of underfill material are 63, 70, and 75 ppm/°C.
High-material module underfill has excellent thermal-cycle performance, good protection for solder-joints and pad connections, and good anti-peeling strength for pads. It’s normally used for isolated packages, such as micro electro mechanical systems (MEMS), land grid array (LGA), BGA, quad flat no-lead (QFN), and molded CSP.
Low-material module underfill has a very high CTE, for example Underfill-B CTE = 31 ppm/°C. It allows the die to have enough movement without breaking the solder joints and exhibits low thermal-cycle performance. It also offers good protection for solder joints and pad connections of a wafer-level packaged (WLP), CSP, and flip chip (FC) die, as well as effective anti-peeling strength for pads. Low-material module underfill is normally used for non-isolated chips, such as those packaged in CSP, WLP, FC, LGA or non-ball style of BGA/CSP. It’s important for the PCB designer to consider some critical aspects when selecting an underfill. First, there is the glass transition temperature (Tg) or that particular temperature when the underfill becomes soft and rubbery. Secondly, the PCB designer must have a good handle on the generic low-ionic requirements for underfills, such as low moisture absorption and low alpha-particle emission.
Micro-BGA and micro-CSP design challenges
Compared with standard surface-mount component board design, the design phase dealing with ultra-fine pitch devices becomes even more critical in successful implementation of micro-BGA devices. A lot can go wrong, and one can end up with an unreliable product that can incur intermittent or latent problems in the field. Extra attention must be paid to the solder joints to ensure trouble-free operation of any device.
At the design outset, the micro-BGA and micro-CSP pads should be created based on the chip manufacturer’s documentation. Pads sizes that are 15% less than the BGA’s ball size have resulted in comparably reliable solder joints. However, the use of non-solder-mask defined (NSMD) pads becomes that much more important with BGA pad sizes that are less than the ball sizes. Statistically, solder joints on the NSMD pads are about three times more reliable than is possible when using solder-mask-defined pads. Another crucial design element deals with selecting the proper PCB surface finish. Today, 98% of the boards using underfill use electro-less nickel immersion gold or ENIG due to its flat surface and excellent solderability without oxidation problems.
Assembly engineering considerations
Techniques used in the underfill process on the assembly floor are far more advanced than those used in the 1960’s flip-chip era, especially since ultra-fine-pitch micro BGAs and micro CSPs are in now growing in popularity. Three major underfill enforcement methods are used today for performance improvement, among other advanced techniques: corner bonding, edge bonding, and full bottom surface bonding.
As shown in Figure 4, corner bonding is used as a low-strength-improvement solution and allows for easy cleaning of the outside areas. Edge bonding provides a medium-strength-improvement solution along with easy cleaning of the edge areas but is more difficult than corner bonding. Full bottom surface bonding provides the maximum-strength-improvement solution. Since it’s difficult to clean the inside areas, this underfill requires a special cleaning process.
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Assembly engineering has a say about selecting the proper underfill for a given PCB application (see Table 1). The following are some general considerations assembly engineering undertakes for underfill selection. As far as thermal-cycle requirements and CTE, if component makers have already performed such protection measures as thermal-cycle isolation, shock protection, and shear strength improvement, PCB-assembly personnel are freed up to concentrate on CTE issues and fab-pad strength-improvement issues.
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It’s also worth noting that when considering lead-free solder ball alloy, certain trade-offs need to be factored in. SAC105 is the second generation of lead-free solder ball alloy. When you compare it with the first generation SAC305, SAC105 has improved mechanical shock resistance but low thermal-fatigue resistance. On the other hand, SAC305 proves to be better on thermal-cycling reliability but isn’t robust enough for drop-test performance. Improved drop-test results are realized with a SAC105 alloy, but the thermal-cycling reliability is sacrificed.
At assembly, a drop test is administered to determine whether a PCB populated with micro CSPs and micro BGAs is able to retain and protect the circuitry after a free fall. It duplicates the rigors associated with manual or mechanical handling at loading and unloading points.
Thermal-cycle requirements
Under normal conditions, a smart phone goes through seasonal temperature changes and warming from the human body and hand, so it has very low requirements for thermal cycle. On the other hand, an altitude-control PCB in a satellite cycles the earth from 100 to 1,000 times daily and will undergo extreme temperature changes and a large number of cyclings. The sun heats it up, and then the earth’s shadow cools it to the extreme–so for this application, the requirements are high for thermal cycling.
WLP, CSP die, and FC die packages such as wireless systems, cellphone CSP/FC projects, satellite navigation, and attitude control systems have the following limited thermal-cycle requirements:
Underfill revisited
It’s seldom that the challenges of cutting edge advances in design can be met with decades-old methods, but the problem of packaging shrinking components and PCBs in today’s portable and mil/aero devices is just such a case. Underfill solves most of these problems nicely without having to reinvent the wheel.
Syed Wasif Ali is an advanced certified designer (CID+) and a layout engineer at NexLogic Technologies, Inc.. He received his BSEE from N.E.D. University of Engineering and Technology in Karachi Pakistan.
Michael Yu is senior manufacturing engineer at NexLogic Technologies. He has extensive experience in process control, SMT process, and manufacturing resources management. He has been in the EMS industry for over 16 years with work experience at Bema Electronics and Pactron Electronics. He has a BS in materials engineering from Shanghai Jiao Tong University and an MS in mechanical engineering from South Dakota School of Mines & Technology.
